1. Field of the Invention
The present invention relates to an image readout apparatus, and more particularly, to an image readout apparatus having a means for storing incident light information. The present invention is applicable to an image readout unit of such as a facsimile apparatus.
2. Description of the Prior Art
A circuit diagram of a prior art image readout apparatus is shown in FIG. 1, in which a light sensor array including nine light sensors is illustratively shown as one example of such image readout apparatuses.
In the figure, three out of nine light sensors E1 to E9 constitute one block, while three blocks constitute a light sensor array. Such is also the case with capacitors C1 to C9 and switching transistors T1 to T9, each corresponding to the respective light sensors E1 to E9 (a common electrode). One electrode of each light sensor E1 to E9 is connected to a power source 101, while the other common electrode consisting of separate electrodes connected via the respective capacitors C1 to C9 is connected to ground.
Among these separate electrodes, the electrodes having the same order in position in respective blocks are connected to one of common lines 102 to 104 via the corresponding switching transistors T1 to T9. Particularly, the first switching transistors T1, T4 and T7 of the respective blocks are connected to the common line 102, the second switching transistors T2, T5 and T8 to the common line 103, and the third switching transistors T3, T6 and T9 to the common line 104. The common lines 102 to 104 are connected to an amplifier 105 via respective switching transistors T10 to T12.
The gate electrodes of the switching transistors T10 to T9 are connected in common collectively for each block, and the commonly connected gate electrodes are connected to a corresponding parallel output terminal of a shift register 106. High level outputs are sequentially delivered from the respective parallel output terminals of the shift register 106, so that the switching transistors T1 to T9 are sequentially rendered conductive collectively for each block.
Each gate electrode of the respective switching transistors T10 to T12 is connected to a corresponding parallel output terminal of a shift register 107. High level outputs are sequentially delivered from the parallel output terminals of the shift register 107, so that the switching transistors T10 to T12 are sequentially rendered conductive at determined timings. The electrodes connected in common of the switching transistors T10 to T12 are grounded via a discharge switching transistor T13. The gate electrode of the switching transistor T13 is connected to a terminal 108.
The operation of the prior art image readout apparatus constructed as above will be explained briefly.
When the light sensors E1 to E9 receive light, the capacitors C1 to C9 store electric charges in accordance with amount of light intensity, respectively. Thereafter, high level outputs from the shift registers 106 and 107 are sequentially delivered at respective determined timings. It is assumed now that high level outputs are delivered from the first parallel output terminals of both registers 106 and 107. Then, the switching transistor T10, connected to the first block switching transistors T1 to T3 via the common line 102, is turned on and the electric charge stored in the capacitor C1 is transferred, via the switching transistor T1, common line 102 and switching transistor T10, to the amplifier 105, thereby outputting the electric charge as image information.
After the electric charge stored in the capacitor C1 is read out, a high level external output is applied to the terminal 108 and the switching transistor T13 is turned on. As a result, the residual electric charge in the capacitor C1 is fully discharged by way of the switching transistor T1, common line 102, switching transistor T10 and hence switching transistor T13.
Succeedingly, by retaining the first parallel output from the shift register 106 at a high level, the parallel outputs from the shift register 107 are sequentially applied to the switching transistors T11 and T12 to turn on the transistors T11 and T12. By doing so, the readout and discharge operations as above are conducted with respect to the capacitors C2 and C3 to thereby sequentially read out the information stored in these capacitors.
After completion of the readout of information from the first block, the shift register 106 is sequentially shifted to conduct the readout of information from the second and third blocks in the similar way as described above. Consequently, the information stored in the capacitors C1 to C9 is read out serially and outputted from the amplifier 105 as image information.
Since the prior art image readout apparatus shown in FIG. 1 has capacitors for storing electric charges, a large output signal can be obtained. Furthermore, it is advantageous in that if the light sensors E1 to E9, capacitors C1 to C9 and switching transistors T1 to T9 are implemented on single substrate made of a thin-film semiconductor, the number of connection points for external circuits can be reduced.
In this connection, however, the thin-film transistor (TFT) has a property that its on-state resistance is high. Therefore, the thin-film transistor is associated with some drawbacks that time constants determined by the capacitances of the capacitors C1 to C9 and the resistances of the corresponding switching transistors T1 to T9 become longer, and that discharge times of the capacitors C1 to C9 also become longer due to the distributed capacitances and resistances of the common lines 102 to 104 and of the switching transistors T10 to T13. Furthermore, there is a problem that the prior art image readout apparatus cannot be operated at a high speed because each of the capacitors C1 to C9 requires a discharge operation after each time it is used in the readout operation.